#ChipScope Core Inserter Project File Version 3.0
#Thu Dec 14 11:48:28 EST 2017
Project.device.designInputFile=C\:\\Users\\cesposito\\Documents\\Xilinx\\uart2bus\\topLevel_cs.ngc
Project.device.designOutputFile=C\:\\Users\\cesposito\\Documents\\Xilinx\\uart2bus\\topLevel_cs.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=C\:\\Users\\cesposito\\Documents\\Xilinx\\uart2bus\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=
Project.filter<10>=intwrite
Project.filter<11>=*data_to*
Project.filter<12>=*data_to_write*
Project.filter<13>=data_to_write
Project.filter<14>=*Write*
Project.filter<15>=*Wr*
Project.filter<16>=*intWr*
Project.filter<17>=*intWrData*
Project.filter<18>=intWrData*
Project.filter<1>=*ad*
Project.filter<2>=*add*
Project.filter<3>=*addr*
Project.filter<4>=*address*
Project.filter<5>=address
Project.filter<6>=*data*
Project.filter<7>=*intr*
Project.filter<8>=*intreaddata*
Project.filter<9>=intreaddata
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=uart clk
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=uart serIn
Project.unit<0>.dataChannel<1>=write_enable_pulse
Project.unit<0>.dataChannel<2>=data_to_write<0>
Project.unit<0>.dataChannel<3>=reset_state
Project.unit<0>.dataDepth=1024
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=5
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=uart serIn
Project.unit<0>.triggerChannel<1><0>=write_enable_pulse
Project.unit<0>.triggerChannel<2><0>=data_to_write<0>
Project.unit<0>.triggerChannel<3><0>=reset_state
Project.unit<0>.triggerChannel<4><0>=Debug_out_OBUF
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCount<1>=1
Project.unit<0>.triggerMatchCount<2>=1
Project.unit<0>.triggerMatchCount<3>=1
Project.unit<0>.triggerMatchCount<4>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchCountWidth<1><0>=0
Project.unit<0>.triggerMatchCountWidth<2><0>=0
Project.unit<0>.triggerMatchCountWidth<3><0>=0
Project.unit<0>.triggerMatchCountWidth<4><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerMatchType<1><0>=1
Project.unit<0>.triggerMatchType<2><0>=1
Project.unit<0>.triggerMatchType<3><0>=1
Project.unit<0>.triggerMatchType<4><0>=1
Project.unit<0>.triggerPortCount=5
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortIsData<1>=true
Project.unit<0>.triggerPortIsData<2>=true
Project.unit<0>.triggerPortIsData<3>=true
Project.unit<0>.triggerPortIsData<4>=true
Project.unit<0>.triggerPortWidth<0>=1
Project.unit<0>.triggerPortWidth<1>=1
Project.unit<0>.triggerPortWidth<2>=1
Project.unit<0>.triggerPortWidth<3>=1
Project.unit<0>.triggerPortWidth<4>=1
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
